A technology disclosed in this specification relates to a fabrication method of a semiconductor device, specifically to a method of forming a source/drain of a microfabricated P channel type MIS transistor in which nickel silicide is used.
In recent years, the structure in which impurity diffusion layers constituting source/drain regions are formed as thinly as possible has been adopted to suppress short-channel effects associated with the microfabrication of transistors. However, the reduction in depth of the impurity diffusion layers results in increase in sheet resistance of the impurity diffusion layers. As a result, it becomes difficult to achieve high-speed operation and low power consumption. Considering this, recent semiconductor devices adopt a silicide formation process in which a metal film is formed on a source/drain region and subjected to a heat treatment to make the metal and silicon react with each other and thereby form a silicide film. Many of the semiconductor devices whose gate length is 100 nm or less particularly adopt a nickel silicide formation process, which has the following advantages: (1) a nickel silicide film can be formed in a low temperature process (<600° C.) which suppresses deactivation of activated impurities and (2) nickel lends itself to formation of shallow junction because less silicon is consumed when nickel is used to react with silicon than other metals for forming silicide under the same sheet resistance.
A semiconductor device fabrication method utilizing a nickel silicide formation process is hereinafter described, with reference to FIG. 5. FIG. 5A to FIG. 5E are cross sections showing a conventional fabrication method of a semiconductor device.
First, as shown in FIG. 5A, an isolation region 1102 is formed in a silicon substrate 1101. Then, an N type well 1103a and a P type well 1103b are formed by photolithography and ion implantation.
Next, as shown in FIG. 5B, a gate oxide film is formed on the upper surface of the silicon substrate 1101 by thermal oxidation, and a non-doped polysilicon film is further formed on the gate oxide film. After that, photolithography and ion implantation are carried out to introduce boron in the non-doped polysilicon film above the N type well 1103a and phosphorus in the non-doped polysilicon film above the P type well 1103b. Then, photolithography and dry etching are carried out to form a gate oxide film 1104a and a P type gate electrode 1105a on the N type well 1103a, and a gate oxide film 1104b and an N type gate electrode 1105b on the P type well 1103b. After that, photolithography and ion implantation are carried out to introduce boron difluoride (BF2) in regions of the N type well 1103a on both sides of the P type gate electrode 1105a, thereby forming P type extension regions 1106a, and introduce phosphorus, thereby forming N type pocket regions 1107a below the P type extension regions 1106a. Similarly, arsenic is introduced in regions of the P type well 1103b on both sides of the N type gate electrode 1105b to form N type extension regions 1106b, and boron is introduced to form P type pocket regions 1107b below the N type extension regions 1106b. 
Then, as shown in FIG. 5C, a TEOS film and a silicon nitride film are formed on the silicon substrate 1101 in order. Etch back is then carried out by anisotropic etch to form a side wall 1110a composed of a TEOS film 1108a and a silicon nitride film 1109a on side surfaces of the gate oxide film 1104a and the P type gate electrode 1105a and form a side wall 1110b composed of a TEOS film 1108b and a silicon nitride film 1109b on side surfaces of the gate oxide film 1104b and the N type gate electrode 1105b. 
Then, as shown in FIG. 5D, photolithography and ion implantation are carried out to introduce boron difluoride (BF2) and boron in the N type well 1103a using a photoresist (not shown), the P type gate electrode 1105a and the side wall 1110a as a mask, thereby forming P type source/drain regions 1111a, and introduce arsenic and phosphorus in the P type well 1103b using a photoresist (not shown), the N type gate electrode 1105b and the side wall 1110b as a mask, thereby forming N type source/drain regions 1111b. 
Then, as shown in FIG. 5E, the impurities introduced in the P type gate electrode 1105a, N type gate electrode 1105b, N type well 1103a and P type well 1103b are activated by a high-temperature, high-speed heat treatment. After that, the upper surface of the silicon substrate 1101 is cleaned with a hydrofluoric acid solution, thereby removing a natural oxide film on the surface of the substrate. Then, a nickel metal film and a titanium nitride metal film are formed on the silicon substrate 1101. The silicon substrate 1101 is subjected to a heat treatment in a nitrogen atmosphere to make the nickel and silicon react with each other. The nickel metal film and the titanium nitride metal film which have not reacted with silicon are removed with a solution in which sulfuric acid and hydrogen peroxide are mixed. The silicon substrate 1101 is again subjected to a heat treatment in a nitrogen atmosphere to form nickel silicide 1112 on the P type gate electrode 1105a, N type gate electrode 1105b, P type source/drain regions 1111a, and N type source/drain regions 1111b. A semiconductor device including a P channel type MOS transistor 1201 and an N channel type MOS transistor 1202 each having nickel silicide is obtained in this way.
However, the P channel type MOS transistor using the nickel silicide formed by the above method has a problem that a junction leakage current flowing from a P type source/drain region to a well increases. The cause was investigated and found to be the nickel silicide formed on the P type source/drain region and having an inverted pyramid shape that invades the P type source/drain region. FIG. 6 is an example of a cross sectional shape of the nickel silicide formed on the P type source/drain region (Reference: The 63rd Annual Meeting of the Japanese Society of Microscopy MG20-E-1430). This kind of abnormal growth of nickel silicide occurs only in a P channel type MOS transistor. Although it has not yet been determined what causes this phenomenon, the following two points are considered to be the cause of the phenomenon: (1) remnant crystal defects in the P type source/drain region before formation of silicide and (2) deformed silicon crystal which is deformed because the P type source/drain region includes a large amount of boron whose atomic radius is smaller than the atomic radius of silicon, and as a result, abnormal diffusion of nickel is apt to occur.
A method for suppressing the abnormal growth of silicide in the P channel type MOS transistor is disclosed in Japanese Patent No. 3033528, for example. The method disclosed is a semiconductor device fabrication method including a step of forming titanium silicide on a silicon crystal containing an impurity element whose atomic radius is smaller than the atomic radius of silicon. In this method, the above impurity element is introduced in a silicon crystal containing an element whose atomic radius is greater than the atomic radius of silicon and which does not cause chemical reaction with silicon and does not generate a level in the silicon. By doing so, distortion of the silicon crystal is corrected. A titanium film is then formed on the silicon crystal and the silicon crystal with the titanium film is annealed to form titanium silicide.